An important aim of on-going research in the semiconductor industry is increasing semiconductor performance while decreasing power consummation in the semiconductor devices. Planar transistors, such as metal-oxide semiconductor field effect transistors (MOSFETs), are particularly well-suited for use in high-density integrated circuits. As the size of MOSFETs and other devices decrease, the dimensions of source/drain regions, channel regions, and gate electrodes of the devices, also decrease. One of the techniques to shrink device sizes is that of shallow trench isolation (STI). The use of STI significantly shrinks the area needed to isolate the transistors better than the local oxidation of silicon (LOCOS) technique. STI provides superior latch-up immunity, smaller channel width encroachment and better planarity. The use of STI techniques eliminates the bird-beak frequently encountered with LOCOS.
In conventional STI formation techniques, the hard mask is formed on a silicon substrate that will form the active silicon regions. The hard mask may be, for example, nitride or other suitable material. After patterning, etching is performed through the openings in the hard mask to create recesses in the active silicon regions of the silicon substrate. An insulating material, such as oxide or other suitable material, is deposited in the recesses on the hard mask. A chemical mechanical planarization is then performed to remove the insulator material on top of the hard mask and planarize the top of the STI region. The chemical mechanical planarization stops on the hard mask. Following the planarization, the hard mask layer is removed from the top of the silicon substrate. When the hard mask is a nitride, for example, this is achieved by etching with hot phosphoric acid.
The STI process described above creates STI regions that extend beyond the top surface of the silicon substrate. A schematic depiction of such an arrangement is shown in cross-section in FIG. 1A. A silicon substrate 10 has an STI region 12 formed as described above. A portion 14 of the STI region extends above the silicon substrate 10 by an amount H. This may be referred to as the step height (H). A polysilicon gate 16 is shown passing over the step 14 created by the STI region 12.
The difference in height between the top surface of the STI region 12 and the top surface of the silicon substrate 10 can result in problems in the photolithographic patterning or etch considerations. In other words, the height of the step can cause pattern integrity issues of the polysilicon gate. These include reduced lithography depth of focus, a variation in line width of the polysilicon, jagged edges on the polysilicon line, etc. See, for example, FIG. 1B which shows a top view of a conventional STI arrangement in which the height of the step causes pattern integrity issues. Additionally, if the step is excessive, polysilicon material can be trapped along the step to thereby cause “stringer” defects. Stringers 18 are schematically depicted in FIG. 1B. Hence, undesirable height of the step may produce pattern integrity issues that reduce the quality of the semiconductor device that is ultimately produced.